I enable eth0 and see transactions on the MDIO bus. I have tried that previously and once againt to verify. I will dig into the phy initialization code to see why it seems to ignore PHY1. Yes, I have tried it, but eth1 still doesn’t work. Hoping to get a pre-release of the I will dig into the kernel code to see if there is a workaround.
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This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped.
I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly.
This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero.
Hoping to get a pre-release of the Reluctant to pursue it as we are not using Petalinux: All forum topics Previous Topic Next Topic. I have looked at the following link, and it appears that the issue of supporting two PHYs was solved in I suspect this is a software issue. However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux?
net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
Add the phy handle to the gem sections: Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. I’ve tried your device tree example as well as different examples found: Check the reset pin to the PHYs.
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 and 1.
This has been tested marveell Zynq Ultrascale with a Daughter card. Link never comes up on eth1, although I can see received packets on the eth1 interface, as if the default PHY configuration is enough to receive packets in some form. Thanks for the information. We aren’t linxu petalinux, but the kernel config stuff all looks the same.
According to a Xilinx FAE: Hope this helps everyone with this problem ChromeFirefoxInternet Explorer 11Safari.
Linux source code: drivers/net/phy/marvell.c (v) – Bootlin
FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: The software doesn’t seem to ,inux anything with it. With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible.
Please upgrade to a Xilinx. Another question if I may, what about the dsa part in the tree, isn’t it required? We are not able to run our dual GEM config. The device tree in the newer kernels uses the MACB drivers.
net: phy: marvell: fix Marvell 88E used in SGMII mode – Patchwork
I haven’t used Zynq before, so maybe this suggestion is not appropriate. However, eth1 still doesn’t work correctly.
Did you try running ping with u-boot? Could you explain how to implement Xilinx provided patch at each these different steps? This patch is not yet available linuux the mainline and is expected to be available in the next release.